Static inverter system



P. E. LoRENTzL-:N ETAL 3,323,033

STATIC INVERTER SYSTEM 7 Sheets-Sheet l` May 30, 1967 Filed Feb. 15,1963 May30, 1967 P. E. LoRENTzEN ETAL sTATIc INVERTER SYSTEM 7sheets-sheet 2 Fld Feb. l5, 1965 INVENTOR:

May 30, 1967,y P. E. LoRENTfzEN ETAL 3,323,033

v l STTIC INVERTER SYSTEM Filed Feb. l5, 1963 7 Sheets-Sheet I5 74 ,l-IIL INVENTORS May 30, 1967 P. E. LoRENTzEN ETAL 3,323,033

STATI C I NVERTER SYSTEM Filed Feb.y l5, 1963 '7 Sheets-Sheet 4 MaY 30,1967 l P. E. LORENTZEN ETAL 3,323,033

sTATrc INVERTER SYSTEM A .7 sheets-sheet 5' Filed Feb. 15. 196s iig-1017- v Y UWENTORS` May 30,1967

*Filed Feb. 15. 1963 P, E. LORENTZEN ETAL STATI C INVERTER SYSTEM 7Sheets-Sheet 7 fzglbf i lg. 15C

INVENTORS add/@ y for producing three-phase controlk signals from3,323,033 f STATIC INVERTER SYSTEM Paul E. Lorentzen,PacificPalisades-and Darrell W. Tesdall, Los Angeles, Calif.,assignorsto Douglas Aircraft Company, Inc., SantaMonica, Calif.

` Filed Feb. 1S, 1963, Ser. No. 258,719

6 Claims. (Cl. 321-5) This invention relates generallyk to invertercircuits and more particularly to a three-phase static inverter circuit.The invention also concerns novel inverter-elements and theirinterconnections and interactions with and in the overall circuit.

An inverter isa device for converting direct current into alternatingcurrent. The devices which can accomplish this include both mechanicaland electronic means. The mechanical type inverter is commonly a rotarymachine such as an inverted synchronousV converter, and the electronictype inverter can include` electronic V-tubes kwhich Iare switched onand off to convert a direct supply current into an alternating outputcurrent. These devices have heretofore been extremely heavy and bulky incomparsion to their power output. This was especially true where athree- Y phaseinverter was concerned. f

A three-phase generator is lapproximately` as heavy and large as acomparable inverter. Because of the relatively large weight and/ or sizerequiredfor either la three-phase generator or inverter to obtain evenreasonable power outputs therefrom, most aircraft except the very largeones, do not carry a three-phase generator or inverter. Threephase poweris desirable in aircraft because certain threephase devices asthree-phase motors are far more efficient and powerfuly (better running)than either af'comparable direct current or single phase motor,especiallyat high altitudes. While practically all aircraft have asource of direct current,y=and many have -a sourceof single phasealternating current, only a relatively few, large aircraft have athree-phase power source. Furthen-thesethreephase power sources havebeen invariably of they very heavy and Ibulky mechanical type generatoror inverter.

It is an object of this invention to'nprovide a threephase staticinverter which` is extremely lightweight and small in size but has acomparatively high, and versatilely useful power output. n

Another object of the invention is to provide a threephase staticinverter which is operable from eithera direct current sour-ce or asingle phase, alternating current source.

Another object of therinventionV is to provide a .static inverter whichcan provide either three-phase or single phase power having waveformsthat arersyrnmertical and do not contain a third harmonic. Y

A further object of this invention is to provide an inverter circuithaving -a well regulated direct voltage source and a repetitivelyoperable short circuit or overload protector. f

A still further object of thisY invention is to provide a staticinverter having an output therefrom-.which eliminates the need forheavy, power -consuming output filters. Another object of the inventionis to provide a highly reliable and precise-frequenry pulse generator ina static inverter, to produce -a correspondingly relifble and precisefrequency output from the inverter. Y Y l y Another object of theinvention is to prfovidelsimple and effective gating means in astaticthree-phase inverter the output of a sequential pulse generator.

3,323,033v Patented May 30, 1967 yICC verter circuit including a directpower supply which is proportionately regulatable or controllable inoutput according to variations ofinverter circuit output, and alsooperable to remove power that energizes the operationally controllingelements of the inverter circuit during inverter overload, a sequentialpulse generator, a gating circuit connected to the generator forproducing three-phase control signals to respective driver stages, andpower output stages driven by the driver stages to produce three-phasequasi square output waves which can be applied to a suitable three-phaseoutput transformer.

This invention possesses numerous other objects and features, some ofwhich together with the foregoing, will become apparent from thefollowing detailed description of an illustrative embodiment of theinvention. The invention will be more fully understood from thefollowing description to :be taken in conjunction with the accompanyingdrawings, in which:

FIGURES lA, 1B and 1C, together show a complete circuity diagram of theillustrative embodiment of the inverter circuit;

FIGURE 2 is a graph illustrating partial formation of a synchronizingsignal used in regulating or controlling the main power supply for theinverter circuit; v

FIGURE 3 is a graph illustrating the full formation of the synchronizingIsignal noted above;

lFIGURE 4 is a graphshowing asawtooth Wave which power supply for theinverter circuit, and the desired elimi- And another object of thisinvention is t-o prvide a objects are preferably accomplished byproviding an innation thereof;

FIGURE 8 is a graph showing the` effect of a successively increasingnumherof bias winding turns on the hysteresis loops of a multiple coretransformer used in a pulse geny erator for the inverter circuit;

FIGURE 9 is a graph illustrating the primary voltage Waveform for thepulse generator transformer;

FIGURES 10A, 10B and 10C are graphs which illustrate the output pulsesfrom the pulse generator;

i FIGURE 11 is a diagram which shows the formation of three phases ofcontrolling signals derived from the gating circuit for the invertercircuit;

FIGURES 12A, 12B and 12C are graphs which illustrate the three-phasevoltages developed across the primary windings of the output transformerfor the inverter circuit; Y

FIGURES 13A, 13B, 13C, 13D, 13E and 13F are graphs which illustrate thecurrent conduction through different power output transistors of theinverter circuit;

FIGURE 14 is a vector diagram showing the threephase line-to-neutralVoutput voltages .from the inverter circuit, and a line-to-line voltagederived from two of the line-to-neutral voltages; and

FIGURES 15A, 15B and 15C are graphs which illustrate the formation orvector addition of two line-toneutral output voltages to produce aline-to-line output voltage. l t y FIGURES 1A, 1B and 1C, together, showan illustrative example of one embodiment of this invention. 'I'hesethree figures may be conveniently viewed in entirety by arranging thefigures in sequential order and connecting the ends of leads which areidentified by the same reference letter respectively together betweenadjacent figures. For example, the ends of leads a, b, c, d, e and j ofFIGURE 3 1A are to be joined to the correspondingly identified lead endsat the left side of FIGURE 1B. Similarly, the ends of the leads a, b, c,d, g, h, z', j, k and l at the right side of FIGURE 1B are to =beconnected t-o the correspondingly identified lead ends indicated inFIGURE 1C.

FIGURE 1A generally shows the input power supply system includingregulation and protective circuits for the inverter circuit. Line power,for example, 115 volts, 60 c.p.s., single phase, is provided atterminals 11 and 13. This voltage is applied through limiting resistorsR1 and R2 to the primary winding Tla of a transformer T1 having itssecondary winding Tlb` connected to input terminals 15 and 17 of a fullwave bridge rectifier 19. Oppositely oriented, series connected Zenerdiodes CR1 and CR2 are connected across the primary winding Tla asshown.

The bridge rectifier 19 has output terminals 21 and 23. The terminal 21is connected to a irst base Qla of unijunction transistor Q1 through aseries resistor R3, and the terminal 23 is connected to lead d and tothe second base Qlb of the unijunction transistor Q1 through a resist-orR4. The emitter Q1c of the unijunction transistor Q1 is connected to the`collector of transistor Q2, and to lead d through capacitor C1.

The lead e is also connected to the base of the tranl sistor Q2. throughtwo series connected capacitors C2 and C3, the latter capacitor C3 beingshunted by resistor R7. The wiper or adjustable tap of the potentiometerR6 is also connected to the base of the transistor Q2. The transistor Q2serves as an adjustable resistor whose resistance is varied according tothe potential on the base ofthe transistor Q2.

Variation of the effective resistance of transistor Q2 varies thecurrent ow through it, and Ihence the charging rate of the capacitor C1.The charging path is from lead e through resistor R5, transistor Q2 andcapacitor C1 to the lead d. When the capacitor C1 is charged to asufficiently high potential, the unijunction transistor Q1 becomesforward biased and permits the capacitor C1 to discharge rapidly throughresistor R4 to produce an output voltage across it.

The line power input terminals 11 and 13 can be also connectedto inputterminals 25 and 27 of a controlled full wave bridge rectiier 29 havingoutput terminals 31 and 33. A thyrector CRS is connected between theoutput terminals 25 and 27, and provides protetction against transientsby ybreaking down and absorbing the very high transients that mayappear. A separate single phase, 60 c.p.s. power source can be connecteddirectly j to input terminals 25 and 27 instead of using the same sourceat terminals Y11 and 13; however, the separate single phase power sourcemust be in phase with that at terminals 11 and 13.

The output terminal 31 is connected to input terminals 25 and 27,through respective diodes CR6 and CR7. The terminals 25 and 27 are,in'turn, connected to output terminal 33 through diodes CRS and CR9,respectively. The output terminal 31 is connected to lead a, and theoutput terminal 33 is connected to lead d and to lead b `through arectifying magnetic amplifier 34. The magnetic amplifier 34 isconventional and is energized by the single phase power from terminals11 and 13. The direct current control winding can consist merely of asingle turn of the output lead b passing around the saturable core ofthe magnetic amplifier 34. The magnitude of the direct current flowingin the output lead b, of course, controls the output from the magneticamplifier 34. The magnetic amplifier 34 includes the usual rectifyingdiodes which are connected to the ends of the output windings providedon the saturable core transformer of the amplifier 34.

The diodes CRS and CR9 are silicon controlled rectiiiers having anode,cathode and gate electrodes. As is well known, the diodes CRS and CR9'are turned on when the gates are made sul'liciently positive withrespect to their cathodes. Once the diodes CRS and CR9 are turned on,they will conduct until anode potential becomes zero or negative withrespect to the cathodes. The diodes are thus similar to thyratrons. InFIGURE 1A, only one of the diodes CRS or CR9 which is then forwardbiased is turned on by a positive gate voltage.

The gates of the diodes CRS and CR9 are connected to the end of resistorR4 tied to base Qlb of the unijunction transistor Q1, and the cathodesare connected to the output terminal 33 whichis tied to the other sideof the resistor R4 through the lead d. Thus, the output voltage acrossthe resistor R4 is used to control the rectified output voltage from thebridge 29. The bridge 29' output passes through the -magnetic ampliiier34 to leads b and a. The direct voltage provided between the leads b anda is, for example nominally 8O volts, and is the basic source of outputpower for the inverter circuit.

If the diodes CRS and CR9 were alternately conducting continuously, theoutput voltage between the leads b and a would have a waveform includinga series of contiguous, positive half cycles of a sine wave. The voltageat the end of one half cycle and, of course, the start of the next halfcycle is zero so that the conducting diode CRS or CR9 will be turned offat these points. Since the output voltage developed across `the resistorR4 is dependent upon the discharge of the capacitor C1 through theunijunction transistor Q1, the start of a charging cycle of thecapacitor C1 should be synchronized with a zero voltage point of theinput signal to the full wave bridge rectifier 29 for proper control ofthe output voltage between leads b and a.

FIGURES 2 and 3 are graphs which illustrate the manner in which asynchronizing signal is obtained for controlling operation of theunijunction transistor Q1 and the start of a charging cycle of thecapacitor C1. The single phase, 60 c.p.s. sine wave signal which isapplied to input terminals 11 and 13, and 25 and 27 is indicated ascurve 35 in FIGURE 2. The effect of the zener diodes CRI and CR2 is toremove peak portions of the positive and negative half cycles. Thisproduces a trapezoidal waveform 37 having positive and negative halfcycles as shown in FIG- URE 2.

The voltage waveform 37 is transformed by the transformer T1 andrectified bythe full wave rectiiier 19 to produce the voltage waveform39 shown in FIGURE 3. This signal appears between the output terminals21 and 23, and is applied to the unijunction transistor Q1 throughresistor R3. The maximum value of this voltage is, for example, 18 voltsand has half cycle notches which drop to zero volt.

FIGURE 4 is a graph which illustratively depicts the charging anddischarging cycles of the capacitor C1. The waveform curve 41 isslightly exaggerated (for clarity of illustration) in that therepetition rate is somewhat reduced from that encountered in practice,and a sudden frequency change at time t1 is shown which does notactually occur but is made for explanatory purposes. A normal repetitionrate, for example, can vary from 360 c.p.s. at full load to c.p.s. atminimum load, approxi- S the capacitor C1 to be rapidly dischargedthrough the transistor Q1 and resistor R4. The voltage on the capacitorC1 drops sharply at the end of the first sawtooth, of

course.

FIGURE 5 is a graph showing a plot of the voltage f developed across theresistor R4 versus time. When the capacitor C1 discharges rapidlythrough the unijunction transistor Q1 and resistorrR4, a voltage pulsesuch as the first one of the pulses 43 is produced across resistor R4and applied to the gates of the diodes CR8 and CR9, turning on the onethat is then forward biased. The discharged capacitor C1 begins tocharge up again and is quickly discharged later as indicated byther/second sawtooth of the curve 41 of FIGURE 4. The second pulse ofthe series of pulses 43 is produced again with the rapid discharge ofthe capacitor C1, and this second pulse is applied without effect to thegates of the alreadyconducting, forward biased diode or the reversedbiased, nonconducting diode..

FIGURE 6.is another graph plotting the `output voltage of the full waverectifier 29 appearingA between leads b and a following the magneticamplifier 34. Curve 45 can be seen to comprise pulses or portions ofhalf cycles of a fully rectified sine wave as indicated by the brokenlines completing each portion of they curve 45. The. curve 4S is zerountil the first pulse'of the series' of pulses 43 is produced. Thiscauses conduction of either'` diode CRS or 1 CR9 so that the 60 c.p.s.singlerphase, sine wave input signal to the rectifier 29 is rectifiedand passed to its output. Thus, the first portion of the rectified halfcycle begins at a magnitude on the first half cycle corresponding to thetime that the first pulse of the series of pulses 43 is produced.

Subsequent pulses 43 appearing during the first half cycle have noeffect, of course, on the now conducting diode CRS or CR9. At the end ofthefirst half cycle, the voltage to the rectifier 29 drops to zero sothat the conducting diode CRS or CR9 is turned off and ceasesconducting.At the same time, the base voltage to the unijunction transistor Q1 alsofalls to zero and conducts to discharge the chargingl capacitor C1.,This isjindicated by the first notch to zero voltage on the curve 39 ofFIG- URE 3. o y

When the unijunction transistor1Q1 conducts, the fourth sawtooth incurve 41 of FIGURE 4 is cut short as shown, to immediately begin a newcharging cycle. Thus, the notches to zero voltage onvcurve 39 of FIGURE3 act to synchronize the charging cycles of the capacitor C1 with thestart of each new half cycle of the input signal to the rectifier 29. Apulse whichV is the fourth one ofthe series of pulses 43 ofFIGURE 5 isproduced with the end of' the fourth sawtooth of curve 41 in FIGURE 4,but this pulse cannot fire or turn on either diode CRS or CR9 becausethe voltage to their anodes is Zero at the end of the first half cycleof the input signal to the rectifier 29. Thus, a new and similar cycleof operation is begun.

It is apparent from the first two pulses or portions of each half cycleof the curve 45 shown in FIGURE 6, that of the potentiometer R6, wouldalter the charging ratey of the capacitor C1. yAssuming that this hadbeen done at time t1, lthe sawtooth waveform curve `41 of FIG- URE 4 maybe changed to that foll'owingthe time. l1 and charging rate of capacitorC1 .is reduced, it is apparent from the first sawtooth after the timekt1 of curve 41 in FIGURE 4, that a longer time is needed for the volt- 6age on the capacitor G1 to reach the voltage V1 at which time theunijunction transistor Q1 i-s forward biased to discharge the capacitorC1.

Discharging of the capacitor C1 produces the first pulse after the timet1 of `the series of pulses 43 of 'FIGURE 5, and this pulse is appliedto turn on one `of the diodes CRS or CR9 as before. However, it canfbeseen in FIGURE 6 that an output voltage between the leads b and a is notproduced until near the end of the sine wave half cycle that is to berectified by the rectifier 29.

The second sawtooth following the time t1 is cut shortk as before due tothe corresponding synchronizing zero voltage notch of curve 3-9 inFIGURE .3. The resulting pulse of the series of pulses 43 lin FIGURE 5does not fire the diodes CRS or CR9 because thevoltage applied to theanodes thereof is then zero as at the end of the first pulsejor portionof the sine wave half cycle. The cycle of operation is then repeated toproduce successive pulses or portions of 4the sine wave half cycleswhich are suitably filtered to produce a lowerV direct voltage thanobtained previously. This is clearly evident by comparing the hatchedarea-s for the two different charging rates illustratively shown andLdiscussed.

The line input terminals 11 and 13 are connected to the primary winding'IZa of a transformer T2 having two secondary windings T2b and T2c asshown in FIGURE 1A. The secondary windings T2b and 'I`2c are connectedto respective full Wave diode rectifiers 47 and 49 which are each partof a regulator circuit for providing respective regulated outputvoltages therefrom. Regulated direct voltages are obtained for supplyingcertain of the control circuits of the inverter circuit. ySince thereare no Vother interacting circuits here with the 6Oc.p.s., single phase,input line voltageon terminals 11 and 13, another separate andindependent input power source may be used, if morey convenient, toproduce the desired,rregulated direct voltages.

The regulator circuit 51 is substantially conventional and only a briefdescription yof it is necessary. The other regulator circuit includingthe rectifier 49` is substantially identical to circuit 51. However,interconnecting with the regulator circuit including the rectifier 49 isa novel short circuit or overload protector. This shortV circuitprotector, except for one resistor R11, includes those elements shown inthe circuit below the regulator circuit 51 which are in addition tothose elements comprising the regulator circuit 51. The description ofthe regulator circuit ,5:1 is applicable' to both regulator circuitsshown in FIG- URE 1A. Y

Briey, the wiper of. potentiometer R9-senses a variation, say, of adecrease of the regulated negative output voltage such that the wiper ofpotentiometer R9 becomes more positive relative to the fixedreferencepvoltage escommon junction between the resistor R10Hand thecol-l tablished by the Zener diode CR-r10 on the emitter of transistorQ3. The positively increased base of transistor Q3 reduces the currentflow through it, and as a consequence, the base of the transistor Q4connected to the lector ofthe transistorQ3 increases negatively.

This causes the transistor Q4 to conduct more'heavily such that thepotential of the base of transistor Q5, which is the series con-trolelement, increases negatively and the effective resist-ance ofthetransistor Q5 is reduced'. The lead d which is negative relative tothe lead e therefore increases negatively to increasethe negative outputvoltage between leads d and e. An increase of the negative outputVoltage produces the opposite effect to regulate the voltage betweenleads d Iand e. The col-lector of tranrhaving a lower frequency orrepetition rate. When the sistor Q5 is norm-ally at -22 volts, forexample, and the emitter thereof, or lead d, is at the regulated 18volts relative to the lead e.

` The regulated output voltage of the regulator 51 is used to supply thetransistor Q2 and charge capaci-tor C1. Current from lead e follows thepath of resistor R5,

transistor Q2, capacitor C1 and to the lead d. The lead c is connectedto the potentiometer R6 through diode CR3, and serves to impress apositive direct voltage which is proportional to the output of theinverter circuit to Ithe potentiometer relative to the lead d. Thissample voltage of the output of the inverter circuit produces a voltageof 22 volts, f-or example, on lead c for application to thepotentiometer R6.

If the output of the inverter circuit should iiuctuate as in causing arise in output, for example, the voltage on the lead c increases so thatthe voltage on the base of the transistor Q2 also increases to increasethe effective resistance of the transistor. This, of course, lowers thecharging rate of capacitor C1 and produces the effect il- -lu'strated inexaggerated form in FIGURE 6. The result is that the basi-c supplyvoltage for the inverter circuit between leads b and a is decreased toits original level. A similar corrective action takes place fordecreases instead of increases of output voltage from the invertercircuit.

'Iihe output of the inverter circuit is a three-phase alternatingvoltage, and the positive direct volta-ge sample thereof is derivedthrough a suitable three-phase stepdown transformer (T8) connecting witha three-phase rectifier (135), in a manne-r as will be described ingreater detail later. When the inverter circuit is first turned on, -its-output builds up comparatively slowly and the sample voltage on lead clikewise rises relatively slowly.

The sample voltage on lead c doe-s not .rise suiiiciently fast toincrease the effective resistance of transistor Q2 adequately such thatthe conducting durations of the diodes CRS or CR9 and thus the outputfrom the rectifier 2-9 for the usual initial, transient surge cycles aremade short enough to prevent the ini-tial power surges and transientsfrom appearing at the output of the rectifier 29 and leads b and a. Ifthese initial transient surges are conducted to any extent through therectifier 2-9, even for relatively short durations, the very high peaksand overshoots would burn out or damage the transistors and componentsthat are supplied by leads b and a.

FIGURE 7 is a graph which shows a plot of the initial transient surgevoltage which would appear on leads b and a because of the slow build-upof the output voltage of the inverter circuit, and of the sample directvoltage derived therefrom and which appears on lead c. Curve 53indicates the high transient voltage that initially appears beforecontrol can be established to obtain the nominal 80 volts that normallyappears on the leads b and a. By preventing high transient overshoots sothat the direct voltage on leads b and a builds up gradually asindicated by curve 55, no damage will be done to the transistors andcomponents supplied through leads b and a.

In order to eliminate the initial transient surges, the regulated outputvoltage from the regulator 51 in FIG- URE 1A is utilized. This regulatedoutput voltage is developed very quickly in comparison with the outputfrom the inverter circuit. The voltage on lead e, positive with respectto the lead d, is impressed across the potentiometer R6 through thediode CR4 and is Valso applied directly to the base of the transistor Q2through the network including series capacitors C2 and C3, and resistorR7 shunting the latter capacitor.

When the inverter circuit is first energized, the series capacitors C2and C3 are unchanged and act as a short to apply the relatively positivevoltage on lead e to the base of the transistor Q2. This produces a higheffective resistance of the transistor Q2 and the diodes CRS and CR9will not be fired until the capacitor C1 is slowly charged to thenecessary potential. Of course, after the capacitors C2 and C3 are fullycharged, this network has no further effect on the transistor Q2 and thesample direct voltage on lead c should 'be then built up to assumecontrol.

However, if the capacitance of the capacitors C2 and C3 are made largeenough to be effective until the voltage on lead c is sufficiently builtup, the sensitivity of the control system involving transistors Q1 andQ2, and capacitor C1 is too low, having too `slow a response time forproper control of iiuctations of output of the inverter circuit.

For this reason, the diode CR4 is provided to apply the voltage (18volts, for example) from lead e to the potentiometer rR6 after thecapacitors C2 and C3 are fully charged but still before the voltage (22volts, for example) on lead c -has been adequately built up. Thisensures that a reasonable voltage will be provided on the base of thetransistor Q2 throughout the initial starting period.

It was previously mentioned that the circuitry shown below the firstregulator 51 in FIGURE 1A includes another regulator which issubstantially similar to the regulator 51 and also a short circuit oroverload protector. The output of the second regulator is between theleads e and f wherein lead 7" is positive relative to the lead e. Sincethe lead d is negative relative to the lead e, lead e is the commonoutputlead for the two regulators.

The magnetic amplifier 34 is the short circuit or excessive currentsensing element for the short circuit or overload protector. The shortcircuit protector shuts off the inverter circuit by removing theregulated output voltage between leads f and e suppling inverter circuitcontrol elements for a predeterimned duration and then automaticallyreturns this regulated output voltage. However, if the short orexcessive current condition is still present, the protector will repeatits operation or until the short or excessive current condi-tion isremoved.

The short circuit or overload protector includes, in addition to itssensing element 34, a transistor Q6, silicon controlled rectifier CR11,resistor R11, unijunction transistor Q7, capaci-tors C4 and C5, zenerdiode CR12, and resistors R12, R13, R14 and R15. These elements areconnected to the regulator below regulatorSl as Vshown in FIGURE 1A. Ifa short ocurs in the output -of the inverter circuit or any partaffecting current -fiow `through the sensing element 34, excessivecurrent is drawn therethrough which increases the voltage output to, forex`` ample, .5 volt which activates the short circuit protector.

It can be seen in FIGURE 1A that the emitter of the transistor Q6 isconnected to lead f, and the collector is connected to the anode of thesilicon controlled rectifier CR11. The cathode of the rectifier CR11 isconnected to one of the output leads from sensing element 34, the otheroutput lead of which is connected to the gate of the silicon controlledrectifier CR11. The collector of the regulator series element,transistor Q8, is connected to one end of the capacitor C4 and resistorR12. The collector of the transistor Q8 is also connected to the base oftransistor Q6 through resistor R15, and the other end of resistor R12 isalso connected to the base of the transistor Q6 through a capacitor C5.

The other end of the capacitor C4 is connected to the emitter ofunijunction transistor Q7 and to one end of a resistor R13. The resistorR12 is also -connected to one base of the unijunction transistor Q7, theother base of which is connected to one end of a resistor R14. The otherends of the resistors R13 and R14 are connected to the cathode of thesilicon controlled rectifier CR11 through the Zener diode CR12. Thecathode of the rectifier CR11 is also connected to the base oftransistor Q9 and one end of a resistor R11, the other end of which isconnected to the collector lead of the transistor Q8.

The regulator shown in FIGURE 1A just below the regulator 51 functionsin like manner as the regulator 51. However, when excessive currentflows through the sensing element 34, the voltage output from it issufficient to fire the silicon controlled rectifier CR11. The transistorQ6 is biased through resistor R15 to conduct so that current flowsthrough the transistor Q6, rectifier CR11 and resistor R11. The base oftransistor Q9 approaches the positive potential of lead f and asuiiiciently high voltage 9 is developed across the resistor R11 which`is enough to break down the zener diode CR12. When the base of thetransistor Q9 becomes highly positive, the base of the transistor Q8also becomes highly positive to eut ofi:l the transistor Q8. Thisremoves the +18 volts regulated output voltage.

The voltage developedr across resistor :R11 is applied across theparallel branches including resistor R13y in series with capacitor C4,and the series connected resistor R14, unijunction transistor Q7 andresistor R12. The Zener diode CR12 breaks |dow-n when the voltageapplied to it is approximately volts, for example. The capacitor C4charges for about 13 seconds, for example, until it reaches a voltagewhich forward biases the unijunction transistor Q7 and rapidlydischarges the capacitor C4 through resistor R12. A positive voltage isthus obtained and applied through capacitor C5 to the base of thetransistor Q6 turning off the same. This, of course, cuts off thesilicon controlled rectifier CR11 and returns the regulator systemincluding full wave rectifier 49 back to normal operation.

However, the rectifier CR11 is again fired to repeat the cycle ifexcessive current is still owing through they sensing element 34. Thissensing element can incidentally be simply a piece of nichrome wire, orvery small resistor if the lead d did not connect with the output of therectier 29. That is, a small resistor can be'used instead of magneticamplifier 34 in lead b if the voltage regulator 51 output was not usedto energize the control circuit .including the transistors Q1 andkQ2`which control the full wave rectifier 29. It is also obviouslypossible to include a current sensing element (not shown) in series withthe rectifier CR11 to trigger a suitable alarm whenever excessivecurrent Hows through sensing element 34.

Alternatively, the resistor R11 could include the resistance of awarning lamp or relay coil which would have such threshold values thatthe lamp is not visibly lit or the relay pulled in until the rectifierCR11 is fired and conducting. Such a relay coil, when Vsufficientlyenergized, would actuate a relay (no-t shown) to remove inverter powerand inactivate the inverter circuit. The relay is, of course, releasedfor normal operation current conduction through resistorR11.

FIGURE 1B shows a magnetic sequential pulse'generator 57 including asaturable core transformer T3,Ya gating circuit 59 and (three) driverstages 6'1'forfthe inverter circuit. The pulse generator 57-producesoutputs similar to a conventional ring counter. vThe pulse ygenerator 57operates on the principle that the voltage developed in an outputwinding (of transformer T3) is proportional to the ux changes inthe'magnetic core on which the Voutput winding isy wound. The generator57 is basically Va magnetically coupled multivibrator 63 having asatura- 'URE 1B is for low repetition rates or frequencies andrelatively long output pulse widths ork durations. However, much higherrepetition rates or frequenciesk and much shorter pulse widthsorfdurations canbe easily ob` ,'65

tainedby use, for example, of small ferrite cores. The transformer T3has three toroidal cores, `for example, which are preferably stacked oneon topl ofthe other as schematically indicated in FIGURE 1B. A single,separate output winding is wound around each'of'the cores and,additionally, a singleA bias winding is also Wound aroundy each of thecoresbut these 'bias windings are connected in series. The primarywindings T311 and T3b, andthe feedback windings T30 and T3`d are woundaround the entire stack of cores. y ff The leads a, `b,'c and d do notconnect with any coniponents in FIGURE 1B. However, the leads e and fare connected to provide their regulated output voltage to the pulsegenerator 57 and the driver stages 61. The lead f is positive withrespect to the lead e, of course. The common junction of the primarywindings T3@ and T3b is connected to lead f, and the collectors oftransistors Q10and Q11 are connected to lead e as shown.

The common junction of primary winding T3a and feedback winding T3c isconnected to the emitter of the transistor Q10, and the common junctionof the primary winding T3b and feedback winding T3d is similarlyconnec-ted to the emitter of the transistor Q11., The free end of thefeedback winding T30 is connected to the base of the transistor Q10through a speed-up network including resistor R17 shunted by capacitorC6. Similarly, the free end of the feedback winding T3d is connected tothe base of the transistor kQ11 through another speed-up networkincluding resistor R18y shunted by capacitor C7. The base of thetransistor Q10r is also connected to lead e through start resistor R19.

'The common junction between primary winding T3a an-d feedback windingT3r,` is connected to one end of bias ywi-nding T3e through a limitingresistor R20. The other end of the bias Winding T3e is connected throughbias Winding T3]c to one end of bias winding T3g, the other end of whichis connected to the common junction between primary windingT3b andfeedback winding T3d. As indicated in FIGURE 1B, the bias windings havesuccessively increasing numbers of turns.

For example, -bias winding T3e can have 10% of the number of turns of aprimary winding, bias winding T3f can have 20%, and bias winding T3g canhave 30%. Output windings T3ih, T31' and T31' have their center tapsyconnected to lead e, and are respectively wound on the Same cores asthe bias windings T3e, T3f and T3g. Alternatively, the first biaswinding T3e can be completely eliminated so that bias winding, T3f canstart with the 10% figure, and bias winding T3g can be increased anequal increment for a 20% figure. The elimination of the first biaswinding T3e would remove any offset or displacing eifect on thehysteresis loop for the first core, and the loop would be centerednormally along the abscissa ampere-turn axissymrnetrically on theordinate iiux` axis.

The bias winding T3@` and output windings T3h are wound on core 65, biaswinding T3f and output winding T31' on core 67, and `bias winding T3gand output winding T31' on core 69. The bias windings T3e, T3f and T3ghave successively increasing numbers of turns as mentioned previouslyand indicated in FIGURE 1B. The effect of -such bias windings is tooffset or displace the hysteresis 'loops progressively from theordi-nate ux axis along the abscissa ampere-turn axis. The result isthat outputs of the cores are progressively 'delayed and energizedk insequence with increasingy magnetizing current.

FIGURE 8 is a graph in which ux p is plotted against magnetizingampere-turns N-Im, illustrating the effect of the bias windings onthehysteresis loops of each of the cores 65, 67` and 69. A positive biascurrent through the series bias windings T3e, T3f and T3g would displaceYthe hysteresis loops to the right of the flux ordinate axis, and

a negative bias current resulting from a switch of conduction of thetransistors Q10 and Q11 would displace the hysteresis loops for thecores 65, 67` and 69 to the left of theux ordinate axis as indicated inFIGURE 8. Positive output pulses, across an output winding, are producedfor a positive magnetizing current Im, and negative output pulses areproduced after the magnetizing'current `drops to zero and becomessufficiently negative to overcome the Veffect of the then negative biascurrent. rPhe magnitude of these output pulses across an output windingare, for example, 12 volts, or 6 volts relative to its center tap or thelead e.

FIGURE 9 is a graph whichis a plot of primary winding voltage producedkby the multivibrator 63 versus time.

This is the usual Waveform produced in a magnetically coupledmultivibrator as is well known. The various points 71, 73, 75, 77, 79,S1, 83, S5, 87, 89, 91, 93, 95, 97 and 99 indicated on the hysteresisloops shown in FIGURE 8 are also indicated along the Waveform 101 togenerally inter-relate the input voltage on the primary windings T3a and'I`3b of the transformer T3 with the hysteresis loops of the cores 65,67 and 69. It is noted that the displacement of the individualhysteresis loops do not etiect operation on the primary side of thecircuit since the voltage produced in the primary windings is equal tothe sum of the voltages produced in the individual output windings timesthe turns ratio.

FIGURES A, 10B and 10C are graphs which illustrate the output signalsfrom the cores 65, 67 and 69, respectively. As is evident from thesefigures, the various numbers interrelating the points on the hysteresisloops in FIGURE 8 with points along the waveform 101 in FIGURE 9 arealso shown on certain of the pulses of the series of pulses 103, 105 and107 in FIGURES 10A, 10B and 10C, respectively. The frequency of thesquare wave 101 is, for example, 400 c.p.s.

At point 71 in FIGURES 8 and 10A, all of the cores 65, 67 and 69 are innegative saturation, As the magnetizing current Im builds up in aprimary winding T3a, for example, point 73 is reached and core 65 isdriven out of saturation. Between points 73 and 75, the ux change incore 65 produces the first pulse of the series of pulses 103 shown inFIGURE 10A, and which appears in the output winding T3h of the yfirstcore 65. As the magnetizin-g current continues to increase, core 65 isdriven into positive saturation and point 77 is reached in core 67.Between points 77 and 79 the ilux changes rapidly until positivesaturation is reached in core 67 This flux change produces the rst pulseof the series of pulses shown in FIGURE 10B, and which appears in theoutput winding T31' of the second core 67. This latter pulse isdisplaced -60 electrical degrees from the former pulse as taken withrespect to the square wave 101.

Similarly, the third core 69 is nally driven from negative to positivesaturation between points 81 and 83, producing the rst positive pulse ofthe series of pulses 107 shown in FIGURE 10C. This pulse, of course,appears in the output winding T31 of the third core 69, and is displaced60 electrical degrees as indicated in FIGURE 9, from the rst pulse ofthe series of pulses 105 of FIGURE 10B. At point 83, all of the cores65, 67 and 69 are in positive saturation, and the magentizing current Imrapidly builds up in the active primary winding T3a of the multivibratorcircuit causing transistor Q10 to drop out of saturation and start thenormal sequence of events leading to the switching oit of transistor Q10and the switching on of the transistor Q11.

When the transistor Q11 is turned on, the polarity of the square wave101 shown in FIGURE 9 is reversed, and the current polarity through theseries connected bias windings T3e, T3f and T3g is reversed whicheffectively switches the individual hysteresis loops from the right tothe left side of the flux qb ordinate axis as indicated in FIGURE 8.Since the magnetizing current Im now builds up in the oppositedirection, the cores 65, 67 and 69 are driven successively from positiveto negative saturation, completing a cycle of events with the productionof the negative pulses respectively following the rst positive pulsesshown in FIGURES 10A, 10B and 10C.

By means of the novel gating circuit 59 shown in FIG- URE 1B, theoutputs of the pulse generator 57 are combined to provide a set ofthree-phase square waves which are used to control and energize thethree driver stages 61. The output Winding T3h has two output leads 103and 105, the output winding T31' has output leads 107 and 109, and theoutput winding T31 has output leads 111 and 113. These leads areconnected to a diode matrix in 12 the ygating circuit 59 which has threepairs of output leads 115 and 117, 119 and 121, and 123 and 125.

The leads 115 and 117 are connected to the bases of driver transistorsQ12 and Q13 through resistors R20 and R21, respectively. The bases ofthese transistors Q12 and Q13 are also connected to lead f (+18 voltsrelative to lead e) through respective resistors R22 and R23. Similarly,leads 119 and 121 are connected to the bases of driver transistors `Q14,and `Q15 through resistors R24 and R25, respectively, and the bases ofthese transistors Q14 and Q15 are also connected to lead f throughrespective resistors R26 and R27. Finally, the leads 123 and 125 areconnected to the bases of driver transistors Q16 and Q17 throughresistors R28 and R29, respectively, and the bases of these transistorsQ16 and Q17 are also connected to lead j through respective resistorsR30 and R31.

During the first positive pulse of the series of pulses 103 shown inFIGURE 10A, the output winding T311 is considered connected to bepositive on lead 103 and negative on the `lead 10S with respect toreturn lead e. When lead 103 is 6 volts positive, diodes CR14, CR15 andCR16 will not conduct, and a low positive voltage (approximately .5volt, for example) on the bases of the transistors Q16, Q15 and1Q12,respectively, will hold these transistors nonconducting.

However, the lead 105 is then 6 volts negative at that time, and diodesCR17, CRIS nd CR19 will conduct and the low positive voltage on thebases of transistors Q17, Q14 and Q13, respectively, becomes negative(of 5.9 volts, for example) to turn on these transistors. Thesetransistors Q17, Q14 and Q13 conduct until the end of the rst pulse ofFIGURE 10A, and then the rst positive pulse of the series of pulses 105of FIGURE 10B becomes effective. The output winding T31' is alsoconsidered to be connected positive on lead 107 and negative on the lead109 with respect to lead e.

In a manner similar to that described above, the transistors Q17, Q14and Q12 are turned on for the duration of the rst pulse of FIGURE 10B.The rst positive pulse of the series of pulses 107 of FIGURE 10C alsorenders the lead 111 positive, and lead 113 negative With respect tolead e. This, then, causes the transistors Q17, Q15 and Q12 to conduct.Following this, the rst negative pulse in FIGURE 10A energizes theoutput winding T3h so that lead 103 is negative, and lead 105 ispositive with respect lto lead e.

The negative lead 103 causes the transistors Q16, Q15 and Q12 toconduct, and thereafter the iirst negative pulse of FIGURE 10B rendersthe lead 107 negative and lead 109 positive with respect to lead e. Thetransistors Q16, Q15 and Q13 are then turned on. Finally, the `negativepulse after the first positive one in FIGURE 10C causes lead 111 to benegative, and lead 113 to be positive with respect to the lead e. Thenegative lead 111 then causes transistors Q16, Q14 and Q13 to conduct.

FIGURE 11 diagrammatically summarizes the action of the pulse series103, 105 and 107 of FIGURES 10A, 10B and 10C in controlling conductionof the driver transistor pairs Q16 and Q17, Q14 and Q15, and Q12 andQ13. The rst positive pulses and the following rst negative pulses ofeach series have been grouped together Within one cycle of theinitiating primary voltage 101 of the transformer T3 from which theseparate output pulses were produced. The resultant control of thetransistors have been arranged into three square waves which are labeledphase A, phase B and phase C. The transistors that are indicated besideeach of these phases of square Waves, are either on or oh according tothe markings on the lsame level or row within the corresponding squarewaves. Those markings which are aligned vertically in the same column,describe the conditions of the corresponding transistors, indicated tothe left side on the same level or row, over a same time interval, ofcourse.

FIGURE 1C illustrates the power output stages that are driven by theoutput of the driver stages 61. From FIG- c 13 URE 1B, it is seen thatthe lead e is connected to the emitters of the transistors Q16 and Q17,Q14 and Q15, and Q12 and Q13, through respective,y positively orienteddiodes CR20. The collectors of these transistors Q12, Q13, Q14, Q15, Q16and Q17 are connected respectively to leads g, h, i, j, k and l whichare continuedon FIGURE 1C. lt can be seen in FIGURE 11 that the outputsVon leads k and l are associated with the phaseA square wave, outputs onleads and j are associated with the phase B square wave, and those onleads g and h are associated with theV phase C square wave.y

s The phase A leads k and l are connected to the ends of the primarywinding T4a of a transformer T4, the phase B leads i and j are connectedto the ends of the primary Winding T5a of a transformer T5, and theAphase C leads g and h are connected to the'ends ofthe primary windingT6a of a transformer T6. The center taps of all of the primary windingsT4a,T5ay and T60: are connected to the lead d which, fromV FIGURE 1A, isseen to be negative with respect to lead e that is connected to theemitters of the driver transistors throughV ythe positively orienteddiodes CR20. v y

The transformer T4 has double secondary `windings T4b and T4c,transformer T5 has double secondary windings TSb and` TSC, andtransformer T6 hasy double secondary windings T6b and T6c. One end ofthe secondary winding T4b is connected to the base of a transistor Q18through a resistor R32, and an opposite polarity end of the secondarywindingl T4c' is similarly connected to the base of a transistor Q19through resistor R33. The other end of the secondary winding T4b isVconnected to the emitter of the transistor Q18, and the otherend of thesecondary winding T4c is connected to the collector of transistor Q18and to the emitter of the transistor Q19.

The secondary windings TSb and T5cl are similarly connected totransistors Q20 and Q21asfare`the secondary windings T6b andT6c`connected to transistors Q22 and Q23, The emitters of thetransistors Q18, Q20 and Q22 are connected together, `and the collectorsof the transistors Q19, Q21 and Q23 are connected together to lead a asshown in FIGURE 1C. Alsothe collector and emitterr respectively of thetransistors Q18 and Q19 are connected to point 127 of the deltaconnected primary windings of transformer T7, the collector and emitterrespectivelyrof the transistors Q20 and vQ21 are connected to point 129,and the collector and'lemitter respectively of the transistors Q22 andQ23 are connected to point 131. Winding La isr connected betweenpoints127 and 129, winding Lb Yis connected between points 131 and 129,and windingLc is connected between points 127 and 131.

The nominal 80 volts -between leads b and a are filtered by seriesinductor 133 and shunt capacitor C8 and applied between the emitters oftransistors Q18, Q20 and Q22, and the collectors of the transistorsQ19Q21 and Q23 as shown in FIGURE 1C. The secondary windings of thetransformer T7 are Y connected having three-phase output ends orterminals labeled A, qB'and 41C, and a neutral terminal labeled N.Line-to-line output voltage is, for example, 208 volts R.M.S. Thethree-phase output is also fed to a three-phase delta-Y step-downtransformer TS, `andthe output of the transformer T8 is rectified by aconventional three-phase rectifier 135 having a filter capacitor C9included across its output. The leads c and d are connected to theoutput of the rectifierA 135, to provide thersample ofthe output of theinverter circuit for use in'controlling or regulating they output of thecontrolled fullwave bridge rectifier 29 shown inFIGURE 1A as previouslydescribed.

Referring now to both FIGURESk 1C and 1l,.the transistors Q17, Q14 andQ13 are ,turned -on during the time interval Ta. Current flows from theyleade through these transistors to the leads l, iiand hy to energizethe lower halves of the primaryV windings T4a and T6a, and the upper-half of the primary lwinding T5a. The transformers T4, T5 and T6 areconnected with secondary winding polarities such that the powertransistors Q19, Q20 and Q23 will be turned on.

When these transistors Q19, Q20 and Q23 are on, the

` main supply current 'from lead b, after filtering, flows through thetransistor Q20 to point 129 of the delta connected primary of outputtransformer T7 and through windings La and Lb to points 127 and 131,respectively, and on through the transistors Q19 and Q23 to lead a. Whencurrent flows through the windings La, Lb and Lc in the directions ofthe arrows shown beside each winding in FIGURE 1C, positive voltages areconsidered developed. However, negative voltages are developed in thewindings for current flow in directions which are opposite to thatindicated by the arrows. Y

Thus, during time interval Ta, a positive voltage is developed acrosswinding La, a negative voltage is developedacross winding Lb, and zerovoltage is developed across the winding Lc. Also, it is noted that thetransistor Q20 carries twice the current carried by each ofthetransistors Q19 and Q23 which are essentially connected in parallelpaths during the time interval Ta.

Continuing on to lthe next time interval, they drive transistors Q17,Q14 and Q12 are on during the time interval Tb as indicated in FIGURE11. The leads l, i and g then conduct current to energize thetransformer primary windings T4a and T511 as before, but the currentdirection is reversed in the primary winding T6a from that of theprevious time interval Ta. Transistors Q19 and Q20 will continue to beenergized but transistor Q23 will be turned off and transistor Q22turned on instead.

Supply current from lead b (filtered) is then fed to both transistorsQ20 and Q22 to points 129 and 131, respectively, of the delta primary oftransformer T7 and through the windings La and Lc to point 127 andthence combined through the transistor Q19 back to lead a. A positivevoltage is developed across the winding La, and a negative voltageacross the winding Lc but none across the Winding Lb. The transistor Q19will carry twice the current that each of the transistors Q20 and Q22carries. It should be apparent from the above description, thatcontinuing through the remaining time intervals of Tc, Td, Te and Tf,various combination-s of voltages are developed across the windings La,Lb and Lc ofthe delta connected primary of the output transformer T7.

FIGURES 12A, 12B and 12C illustrate the voltage waveforms 137, 139 and141 which are produced across the respective windings La, Lb, and Lc. Itcan be seen that symmetrical, quasi .square waveform-s are obtainedwhich, because of their respective symmetry, do not have even harmonicsand, further, this particular quasi square waveform does not have anythird harmonics or any odd multiple thereof. The ylowest harmonicpresent is the fifth. As is well known, a third harmonic component cancirculate entirely within fa three-phase delta connected circuit such asthe primary of the output transformer T7.

Since each of time intervals Ta, Tb, Tc, Td, and Te and Tf represents 60electrical degrees, the waveforms 137, 139 and 141 are properlyseparated -by 120 degrees for a three-phase supply. Following the usualmethod for obtaining root-mean-square values, the R.M.S. val-ue of eachof the quasi square waveforms is equal to .816 Vp, y

where Vp is the peak value of the waveform.

FIGURES 13A, 13B, 13C, 13D, 13E and 13F illustrate the current conductedby the transistors Q18, Q19, Q20, Q21, Q22 andV Q23, respectively.Curves 143, 145, 147, 149, 151 and 153 depict the current carried by therespective transistors Q19 through Q23 over the time intervals from Tathrough Tf which covers-a full cycle of the input voltage 101 at theprimary of the transformer T3 shown in FIGURE 1B.

The voltages developed inthe delta connected primary windings La, Lb andLc of the transformer T7 shown in FIGURE 1C are transformed to producethe usual corresponding three phase voltage in the Y connected secondarywinding Ma, Mb and Mc. These are, of course, lne-to-neutral voltageswhich can be identified as qA, B and qsC voltages. Since the originalphases of primary voltages are uniformly separted lby 120 electricaldegrees as shown in FIGURES 12A, 12B and 12C, the corresponding phasesof secondary voltage are also equally separated by 120 electricaldegrees from each other.

FIGURE 14 is a vector diagram illustrating the threephase,line-to-neutral voltages oA, qbB and oC. To obtain line-to-line voltagessuch as from line or terminal B, to line or terminal A, theline-to-neutra-l voltage vector B must be reversed as indicated by thebroken line vector which is -q B, and then vectorially added to theline-toneutral voltage vector A for the line-to-line voltage vector fromline B to line oA. Line-to-line voltages are, as mentioned previously,208 volts R.M.S., for example.

FIGURES 15A, 15B and 15C are graphs which illustrate the vectorialaddition of the voltage phases 11A and -B. The waveform 155 shown inFIGURE 15A is, of course, similar -to waveform 137 of FIGURE 12A. Thewaveform 157 show-n in FIGURE 15B is similar to the negative of thewaveform 139 shown in FIGURE 12B. By adding waveforms 155 and 157together over the corresponding time intervals Ta through Tf, thepeaked, quasi square waveform 159 shown in FIGURE 15C is obtained. Thiswaveform 159 represents the vector sum of the line-to-neutral voltagephases 45A and -B.

As indicated from FIGURE 15C, the three-phase lineto-line outputvoltages from the Y connected secondary win-dings Ma, Mb and Mc of theoutput transformer T7 have symmetrical waveforms which are similar tothat of the illustrative waveform 159. Since the three-phase outputwaveforms are symmetrical, they do not contain any even harmonics. Also,just as the three-phase primary voltages of the output transformer T7,as illustrated by the waveforms 137, 139 and 141 of FIGURES 12A, 12B and12C, the waveform 159 of FIGURE 15C does not have a third harmonic orany odd multiple thereof. As for the wave-forms 137, 139 and 141, thelowest harmonic in the waveform 159 is the fifth.

It is .also apparent from the waveform 159 of FIGURE 15C that theline-to-line output voltages from transformer T7 and therefore theinverter circuit, approximates a sine wave because of the centrally-peaked half waves in the waveform 159. For this reason, it is possibleto use an output voltage with a waveform 159 or three-phase vo-ltages oflike waveforms directly in place of a single phase `sine -wave voltageor three-phase sine wave voltages in driving certain components such asa motor which was designed and constructed for sine wave voltageoperation.

Both types of waveforms such as the waveform 155 shown in FIGURE 15A orthe waveform 159 shown in FIGURE 15C for three-phase voltages willoperate most three-phase loads as well as a sine wave system. A 115volts, three-phase, 400 c.p.s. motor has been operated from both typesof waveforms with no adverse effects. For applications where the outputof the inverter circuit is to be rectified and filtered, the filteringwill also be more easily accomplished with these two types of waveformsthan with 'a rectified three-phase sine wave output.

The peak of each half cycle of the waveform 159 shown in FIGURE 15C istwice the magnitude of its adjacent shoulders. The root-mean-squarevalue for such a waveform 159, as can be determined by squaring theordinates of a cycle of the waveform 1'59, finding the `average area ofthe squared waveform over the cycle, yand finding the `square root ofthe average area, is equal to .707 Vp or one-half the lsquare root of 2times the peak value (Vp) of the waveform 159.

The output transformer T7 is shown in FIGURE 1C as a delta-Y three-phasetransformer. However, the output transformer `can be three-phase Y-Y,delta-delta or Y-delta of course. Y connected secondary windings do havethe advantage of having a neutral connection 16 available, andline-to-neutral or line-to-line `voltages can be utilized as desired orrequired. The neutral connection would, for example, be desirable whenthe inverter circuit is used to power a Y connected l-oad.

Tlhe inverter circuit described above is a high efficiency, precisefrequency three-phase solid state inverter. The inverter is a static,ultra lightweight unit which can advantageously replace the heavy,mechanically rotating inverters. An operational prototype model withoutan output transformer weighs less than 5 pounds, and power outputs up to1.5 kilowatts have been achieved with efiiciencies of over The quasisquare waveform output from the power stages can be used to power lowvoltage loads directly without need of an output transformer such as thetransformer T7. Thus, the windings La, Lb and Lc shown in FIGURE 1C canbe low voltage loads powered directly from the power stages includingthe transistors Q18 through Q23. A quasi square wave output or othergenerally squared waveform which is provided by the unit also eliminatesthe need for heavy, power consuming output filters.

It is to be lunderstood that the example embodiment of the inventiondescribed above and shown in the drawings is merely 4illustrative of,and not restrictive on, the` a pair of oppositely oriented, seriesconnected zener i diodes connected across said primary winding of saidfirst transformer;

a fir-st full wave bridge rectifier connected to said secondary windingof said first transformer for providing a trapezoidal direct currentoutput signal therefrom;

a first unijunction transistor connected in -a first sawtooth generatorcircuit 'having an output connected to control said pair of controlledrectifiers of said controlled bridge rectifier;

a rate transistor connected to said first sawtooth generator circuit forcontrolling the repetition rate of the same according to a sample signalderived from said inverter system output, an increased Asample signaldecreasing the repetition rate which decreases the output power fromsaid controlled bridge rectifier and the trapezoidal output signal fromsaid first transformer acting to synchronize the sawtooth waveforms witheach half cycle of the alternating current power input to saidcontrolled bridge rectifier;

a network including capacitor means and a diode shunting said capacitorme-ans for applying an auxiliary signal to said rate transistor,augmenting control of the repetition rate of said first sawtoothgenerator circuit during initial phases of the sample signal wherebyoutput of said first sawtooth generator circuit can be used to providecontrol of transients initially produced in power drawn from saidcontrolled bridge rectifier by a load connected to said inverter system;

full wave rectifying means connected to said alternating current powersource for providing direct current output power therefrom;

first and sec-ond regulator circuits connected to said full waverectifying means for obtaining regulated negative and positive directvoltages respectively from said regulator circu its,ksaid vsecondregulator an overload-control transistor biased to/,be normallyconductive; Y

an overload controlled rectifier connected in series with said -overloadcontrol transistor `and which is normally non-conducting, saidresistance being connected in series with said overload controltransistor and overload controlled rectifier forming a seriescombination which is connected in said second regulatoi `circuit at apoint before Said series regulating transistor for energization of`suchtseries com bination; c s magnetic `amplifier connected to sense anoverload condition in a power lead from said controlled bridge rectifierand having its output voltage applied to said overload controlledrectifier to render vthe same conductive when such an overload issensed;-

second unijunction transistor connected in a second sawtooth generatorcircuit;

a Zener ydiode connected in series with said second sawtooth generatorcircuit in a series combination which is connected across saidresistance,said series regulating transistor becoming non-conductivelybiased and removing the regulated positive voltage from supplying saidinverter system, said yZener diode breaking down and said secondsawtooth generator circuit being responsively energized when saidoverload controlled rectifier is rendered conductive to i a sequentialpulse generator in-cludinga saturable, multiple core tran-sformer havingprimary and feed-back windings around all the cores, series connectedbias windings of successively increasing ampere-turns on each of certaincores and an output winding for each core, and a pair of transistorsconnecting with said primary and feed-back windings in a multivibrator lcircuit;

diode gating network including a plurality of diodes in which groups ofthree of said diodes connect with said output windings, respectively,for combining sequential signals therefrom into-three phases of outputsignals;

three pairs lof driver transistors, each pair being connected Ito saidplurality of -diodes to apply-the three phases of output signals torespective `pairs yof said driver transistors to control conductionthereof in a corresponding three .phase sequence;

second, third and fourth transformers each having a center tappedprimary winding and double secondary windings, said primary windings ofsaid second, third and fourth transformers being connected to respectivepairs of said driver transistors, and said center taps and commonjunctionbetween Veac'h of said pairs lof driver transistors beingconnected to the negativeregulated direct voltage of said firstregulator circuit; three pairs of powerftransistors adapted tobesupplied by the output power from said controlled bridge rectifier, saidpower transistors of each pair beingr respectively connected to rsaiddouble secondary windings of a corresponding one of said second, third`and fourth transformers 'and are comple-mentarily iescapes 18conductiveand non-conductive in 'response to a corresponding vphase ofthe three phases of output signals, for controlling the direct currentoutput power j from said controlled bridge rectifier applied to saidpower transistors to produce output power signals in accordance withvariations of the three phase sequence; u

three-phase output transformer having a delta connected `primary and a Yconnected secondary, said delta connected primary being connected tosaid three pairs of .power transistors and energized by the output,power signals thereof;

three-phase sample transformer having ya Y conn nected primary and adelta connected secondary, said Y connected primary being connectedV tothe three-phase output leads of the Y connected secondary of said outputtransformer; and three-phase rectifier connected to the delta connectedsecondary of said sample transformer -f-or providing the sample signalto said rate transistor for controlling the repetition rate of saidfirst sawtooth generator circuit. y

Ant-inverter system comprising:

source of alternating current power;

controlled rectifier connected to said alternating current power sourcefor providing direct current output power therefrom, said controlledrectifier including means for cont-rolling the direct current outputpower from said controlled rectifier; g first transformer including aprimary Winding and a secondary wind-ing;

-zener diode means connected across said pri-mary winding of said firsttransformer; v

first rectifier connected to said secondary winding of said firsttransformer for providing a trapezoidal direct current output signaltherefrom;

first/sawtooth generator circuit having an output consistor,augmentingcontrol of the repetition rate of said first sawtooth.generator circuit during initial phases of the sample signal wherebyoutput ofrsaid first sawtooth generator circuit can berused to providecontrol of transients initially produced Virl-power "drawnfrom saidcontrolled rectifier by a load connected to said inverter system;

rectifying means'connected to said alternating current Y power sourcefor providing direct current output first and second regulator circuitsconnected to. said -rectifying means for obtaining regulated first andsecpower therefrom;

ond direct voltages respectively from said regulator circuits, saidsecond regulator circuit .providing the auxiliary signal to said ratetransistor and including a series regulating-transistor and a resistanceadapted to bias said series reg'ulting transistor to be normallyconductive;

an overload control transistor biased to be normally conductive;

' an overload controlled rectifier connected in series Vwith saidoverload control transistor vand* which is` nor- 'mally 'non-conducting,said resistance being con-` nected in series with said overload controltransistor 19 and overload controlled rectifier forming a seriescombination which is connected in said second regulator circuit at apoint before said series regulating ltransistor for energiZation of suchseries combination;

a magnetic amplifier connected to sense an overload condition in a powerlead from said controlled rectifier and having its output voltageapplied to said overload controlled rectifier to render the sameconductive when such an overload is sensed;

a second sawtooth generator circuit;

a Zener diode connected in series with said second sawtooth generatorcircuit in a series combination which is connected across saidresistance, said series regulating transistor becoming non-conductivelybiased and removing the regulated second voltage from supply-ing saidinverter system, said Zener diode breaking down and said second sawtoothgenerator circuit being responsively energized when said overloadcontrolled rectifier is rendered conductive to produce an output signalfrom said second sawtooth generator circuit after a predetermined timeduration;

means coupling the output signal from said second sawtooth generator tosaid overload control transistor for stopping conduction htereof wherebyconduction of said overload controlled rectifier is also stopped toagain bias said series regulating transistor to be coducting;

a sequential pulse generator including a saturable, multiple coretransformer having primary and feedback windings around all the cores,series connected bias windings of successively increasing ampere-turnson each of certain cores and an output winding for each core, and a pairof transistors connecting with said primary and feedback windings in amultivibrator circuit;

a diode gating network including a plurality of diodes connecting withsaid output windings, for combining sequential signals therefrom intothree phases of output signals;

three pairs of driver electronic devices, each pair being connected tosaid plurality of diodes to apply the three phases of output signals torespective pairs of said driver devices to control conduction thereof ina corresponding three phase sequence;

second, third and fourth transformers each having a center tappedprimary winding and double secondary windings, said primary windings ofsaid second, third and fourth transformers being connected to respectivepairs of said driver devices, and said center taps and common junctionbetwen each of said pairs of driver devices being connected to theregulated first voltage of said first regulator circuit;

three pairs of power electronic devices `adapted to be supplied by theoutput power of said controlled rectifier, said power devices of eachpair being respectively connected to said double secondary windings of acorresponding `one of said second, third and fourth transformers and arecomplementarily conductive and non-conductive in response to acorresponding phase of the three phases of output signals, forcontrolling the direct current output power from said controlledrectifier applied to said power devices to produce output power signalsin accordance with variations of the three phase sequence;

a three-phase step-up output transformer having a primary and asecondary, said output transformer primary being connected to said threepairs of power devices and energized by the output power signalsthereof;

a lthree-phase step-down sample transformer having a primary and asecondary, said sample transformer primary being connected to thethree-phase output leads of the secondary of said output transformer;and

20 three-phase rectifier connected to the secondary of said sampletransformer for providing the sample signal to said rate transistor forcontrolling the repetition rate Iof said first sawtooth generatorcircuit.

An inverter system comprising: source of alternating current power;controlled rectifier connected to said alternating current power sourcefor providing direct current output power therefrom, said controlledrectifier including means for controlling the direct current outputpower from said controlled rectifier; first transformer including aprimary winding and a secondary winding;

Zener diode means connected across said primary wind-A ing of said firsttransformer;

first rectifier connected to said secondary winding of said firsttransformer for providing a tra-pezoidal direct current output signaltherefrom;

first sawtooth generator circuit having an output connected to controlsaid power controlling means lof said controlled rectifier;

rate transistor connected to said first sawtooth generator circuit forcontrolling the repetition rate of the same according to ,a samplesignal derived from said inverter system output, :an increased samplesignal decreasing the repetition rate which decreases the output powerfrom said controlled rectifier and the trapezoidal output signal fromsaid first transformer acting to synchronize the sawtooth waveforms witheach cycle of the alternating curent power in.- put to said controlledrectifier;

means for applying an auxiliary signal to said rate transistor,augmenting control of the repetition rate of said first sawtoothgenerator circuit during initial phases of the sample signal wherebyoutput of said first sawtooth generator circuit can be used to provideycontrol of transients initially produced in power drawn from saidcontrolled rectifier by a load connected to said inverter system;

rectifying means connected to said alternating cur rent power source forproviding direct current outJ put power therefrom;

first and second regulator circuits connected to said rectifying meansfor obtaining regulated first and second direct voltages respectivelyfrom said reg= ulator circuits, said second regulator circuit proaviding the auxiliary signal to said rate transistor and including aseries regulating transistor and a re- `sistance adapted to bias saidseries regulating trana sistor to be norm-ally conductive;

an overload control transistor biased to be normally conductive;

an overload controlled rectifier connecte-d in series with said`overload control transistor and which is normally non-conducting, saidresistance being connected in series with said overload controltransistor and overload cont-rolled rectifier forming a seriescornbination which is connected in said second regulator circuit at apoint :before said series regulating transistor for energization of suchseries combination; magnetic :amplifier connected to sense an overload'condition in a power lead from said controlled rectifier [and havingits output voltage applied t-o said overload controlled rectifier torender the same conductive when such an overload is sensed;

second sawthooth generator circuit;

la Zener ydiode connected in series with said second sawt-ooth generatorcircuit in a series combination which is connected across saidresistance, said series regulating transistor becoming non-conductivelybiased and removing the regulated second voltage from supplying saidinverter system, said Zener diode breaking down and said second sawtoothgenerator circuit being responsively energized when said overloadcontrolled rectifier is rendered conductive to "produce an output signalfrom 'said second sawtooth generator circuit after a predetermined timeduration;

means coupling the output signal from said second saw-tooth generator tosaid overload control transistor for stopping conduction thereof wherebyconduction of said overload controlled rectifier is also stopped toyagain bias said series regulating transistor to be conducting; i

a sequential pulse generator including a saturable, multiple coretransforme-r having primary and feedback windings -around all the cores,ser-ies connected bias windings of successively increasing ampere-turnson each `of certain cores and an .output winding for each core, and apair of transistors connecting with said primary and feedback windingsin a multivibriator circuit; Y

means for combining the sequential signals from said output windingsinto three phases of output signals;

three pairs of drive-r transistors, each pair being connected to saidplurality of diodes to apply the three phases of output signals to.respective pairs of said driver transistors to control conductionthereof in a corresponding three phase sequence;

second, third and fourth transformers each having a center t-appedprimary winding and double secondary windings, said primary windings ofsaid second, third and fourth transformers being connected to respectivepairs of said driver transistors, kand said center taps Iand commonjunction Ibetween each of said pairs of driver transistors being-connected to the regulated first ydirect voltage of said iirstregulator circuit; A

three pairs of power'transistors adapted to be supplied by the outputpower of said controlled rectifier, said power transistors of each pair.being respectively connected to said double secondary windings of acorresponding one of said second, third and fourth transformers and arecomplementarily conductive and nonconductive in response to acorresponding phase of the three phases of output signals, forcontrolling the direct current output power from said controlledrectifier applied to said power transistors to produce output powersignals in accordance with variations yof the three phase sequence;

output means connected to said three pairs of power transistors forproviding three phase energized output leads; and

t sample means connected to 'the three-phase outputy leads of saidoutput means for providingthesarnple signalV to said rate transistor forcontrolling the repetition rate of said first sawtooth generatorcircuit.

4. An inverter system comprising:

a source of direct current power;

a regulator circuit connectedto said source of direct current power forobtaining a regulated direct volt`- age output;

sensing means including asaturable coretransformer connected to sense anexcessive current condition in a power lead from said source of directcurrent power, to produce kan output signal when the exces. sive currentcondition is sensed; y

a control transistor for controlling the regulated direct voltage outputof said regulator circuit;

means for biasing said control transistorto be no1- mally conductive toprovide the regulated direct voltage output from said regulator'circuit;

means responsive to the outputr signal of said sensing means for causingsaid control transistor to be nonconductive for a predetermined durationtoremove the regulated direct voltage outputi'from said regu- Y latorcircuit for such duration; t a sequential pulse generator including asaturable, multiple core transformer havingprirnary and. feedbackwindings around all the cores, series connected bias 22 windings ofsuccessively increasing ampere-turns on each of certainy cores and anoutput winding for each core, and a pair of transistors connecting withsaid primary and feedback windings in a multivibrator circuit; first,second and third pairs of driver transistors;

means connecting the output windings ofv said pulse ond and thirdtransformers lbeing connected to respective first, second and thirdpairs of said driver transistors, and said center taps and commonjunction between each of said pairs of driver transistors beingconnected to the regulated direct voltage of said regulator circuit;iirst, second and third pairs of power transistors adapted to besupplied by said source of direct current power, said power transistorsof each pair being respectively connected to said double secondarywindings of a corresponding one of said first, second and thirdtransformers and a-re complementarily conduc- Vtive and non-conductivein response to a corresponding phase lof the three phases of outputsignals, for controlling the direct current output power from saidsource applied to s-aid power transistors to produce output power to aload in accordance with variations of the three phase sequence; and

r output meansconnected to said three pairs of power transistors forproviding three phase energized output leads adapted to :be connected toa three phase lo'ad.

5. An inverter system comprising:

a source of direct current power;

a regulator circuit connected to said source of direct current power forobtaining -a regulated direct v'oltage output;

f sensing means including a saturable core transformer connected tosense an excessive current conditiony in a power lead from said sourceof direct current l power, to produce anV output signal when theexcessive current condition is sensed;

-a` control transistor for controlling the regulated drect voltageoutput ofV said regulator circuit;

means for biasing said control transistor to lbe normally conductive toprovide the regulated direct voltage output from said regulator circuit;

means responsive to the output signal of said sensingV a sequentialpulse generator including a saturable, multiple core transformer havingprimary and feedback windings around all the cores, series connectedbias windings of successively increasing ampere-turns on each of certaincores yand an output winding for each core, and a pair of transistorsconnecting with said primary and feedback windings in a multivi- :bratorcircuit;

a three pairs of driver transistors; t

means connecting the output windings of said pulse generator torespective pairs of said driver transistors y to apply the sequentialsignals from said pulse gen-v erator in three phases of output signalsthereto, to

control conduction of said driver transistors in a three phase sequence;

three transformers each having a center tapped primary winding anddouble secondary windings, said primary windings of said transformersbeing con- 23 nected to respective pairs of said driver transistors, andsaid center taps and common junction between each of said pairs ofdriver transistors being connected to the regulated direct voltageoutput of said regulator circuit; and

three pairs of power transistors adapted to be supplied by said sourceof direct current power, said power transistors of each pair beingrespectively connected to said double secondary windings of acorresponding one of said three transformers and are complementarilyconductive and non-conductive in response to a corresponding phase ofthe three phases of output signals, for controlling the direct currentoutput power from said source applied to said power transistors toproduce output power to a load in accordance with variations of thethree phase sequence.

6. An inverter system comprising:

a source of direct current power;

a regulator circuit connected to said source of direct to controlconduction of said driver transistors in a three phase sequence;

three transformers each having a center tapped primary winding anddouble secondary windings, said primary windings of said transformersbeing connected to respective pairs of said driver transistors, and saidcenter taps and common junction between each of said pairs of drivertransistors being connected to the regulated direct voltage output ofsaid regulator circuit; and

three pairs of power transistors adapted to be supplied by said sourceof direct current power, said power transistors of each pair beingrespectively connected to said double secondary windings of acorresponding one of said three transformers and are complementaryconductive and non-conductive in response to a corresponding phase ofthe three phases of output signals, for controlling the direct currentoutput power from said source applied tosaid power current power forobtaining -a regulated direct voltage output;

sensing means including a saturable core transformer connected to sensean excessive current condition in a power lead from said source ofdirect current power, to produce an output signal when the eX- 25transistors to produce output power to a load in accordance withvariations of the three phase sequence.

References Cited UNITED STATES PATENTS cessive current condition issensed;` 9531735 9/1960 Schmidt 321-5 control means for controlling theregulated directed 219921410 7/1961 Gfoth et aL 307-885 voltage outputof said regulator circuit, said control 31046412 7/1962 Selke. 321-14 Xmeans being responsive to the output signal of said 3,052,833 9/1962Coohdge et 31- 321-5 sensing means for causing the removal of the regu-3,060,363 10/1962 Jens@ 321-5 lated direct voltage output from saidregulator cir- 310911729 5/1963 Schmldt 321-5 cuit for -a predeterminedduration; 3,098,949 7/1963 Goldberg 317-33 a sequential pulse generatorincluding a saturable, mul- 3,111,632 11/1963 Murphy 331-113 tiple coretransformer having primary and feedback 3,114,098 12/ 1963 RallO et al.321-18 windings around all the cores, series connected bias 3,116,44612/ 1963 Healey 321-18 windings of successively increasing ampere-turnson 3,127,576 3/1964 Haynard 331--113 each of certain cores and an outputwinding for each 3,132,287 5/ 1964 Yarbrough 317--33 core, and a pair oftransistors connecting with said 3,168,692 2/1965 Lilienstein 321 5primary and feedback windings in a multivibrator 3,177,420 4/1965Bal-ber et aL 321 7 wenn; 3,196,337 7/1965 Enron et a1. 321-45 threepairs of driver transistors;

means connecting the output windings of said pulse generator torespective pairs of said driver transistors to apply the sequentialsignals from said pulse generator in three phases of output signalsthereto,

JOHN F. COUCH, Primary Examiner.

LLOYD MCCOLLUM, Examiner.

I. C. SQUILLARO, W. H. BEHA, Assitsamt Examiners.

6. AN INVERTER SYSTEM COMPRISING: A SOURCE OF DIRECT CURRENT POWER; AREGULATOR CIRCUIT CONNECTED TO SAID SOURCE OF DIRECT CURRENT POWER FOROBTAINING A REGULATED DIRECT VOLTAGE OUTPUT; SENSING MEANS INCLUDING ASATURABLE CORE TRANSFORMER CONNECTED TO SENSE AN EXCESSIVE CURRENTCONDITION IN A POWER LEAD FROM SAID SOURCE OF DIRECT CURRENT POWER, TOPRODUCE AN OUTPUT SIGNAL WHEN THE EXCESIVE CURRENT CONDITION IS SENSED;CONTROL MEANS FOR CONTROLLING THE REGULATED DIRECTED VOLTAGE OUTPUT OFSAID REGULATOR CIRCUIT, SAID CONTROL MEANS BEING RESPONSIVE TO THEOUTPUT SIGNAL OF SAID SENSING MEANS FOR CAUSING THE REMOVAL OF THEREGULATED DIRECT VOLTAGE OUTPUT FROM SAID REGULATOR CIRCUIT FOR APREDETERMINED DURATION; A SEQUENTIAL PULSE GENERATOR INCLUDING ASATURABLE, MULTIPLE CORE TRANSFORMER HAVING PRIMARY AND FEEDBACKWINDINGS AROUND ALL THE CORES, SERIES CONNECTED BIAS WINDINGS OFSUCCESSIVELY INCREASING AMPERE-TURNS ON EACH OF CERTAIN CORES AND ANOUTPUT WINDING FOR EACH CORE, AND A PAIR OF TRANSISTORS CONNECTING WITHSAID PRIMARY AND FEEDBACK WINDINGS IN A MULTIVIBRATOR CIRCUIT; THREEPAIRS OF DRIVER TRANSISTORS; MEANS CONNECTING THE OUTPUT WINDINGS OFSAID PULSE GENERATOR TO RESPECTIVE PAIRS OF SAID DRIVER TRANSISTORS TOAPPLY THE SEQUENTIAL SIGNALS FROM SAID PULSE GENERATOR IN THREE PHASESOF OUTPUT SIGNALS THERETO, TO CONTROL CONDUCTION OF SAID DRIVERTRANSISTORS IN A THREE PHASE SEQUENCE; THREE TRANSFORMERS EACH HAVING ACENTER TAPPED PRIMARY WINDING AND DOUBLE SECONDARY WINDINGS, SAIDPRIMARY WINDINGS OF SAID TRANSFORMERS BEING CONNECTED TO RESPECTIVEPAIRS OF SAID DRIVER TRANSISTORS, AND SAID CENTER TAPS AND COMMONJUNCTION BETWEEN EACH OF SAID PAIRS OF DRIVER TRANSISTORS BEINGCONNECTED TO THE REGULATED DIRECT VOLTAGE OUTPUT OF SAID REGULATORCIRCUIT; AND THREE PAIRS OF POWER TRANSISTORS ADAPTED TO BE SUPPLIED BYSAID SOURCE OF DIRECT CURRENT POWER, SAID POWER TRANSISTORS OF EACH PAIRBEING RESPECTIVELY CONNECTED TO SAID DOUBLE SECONDARY WINDINGS OF ACORRESPONDING ONE OF SAID THREE TRANSFORMERS AND ARE COMPLEMENTARYCONDUCTIVE AND NON-CONDUCTIVE IN RESPONSE TO A CORRESPONDING PHASE OFTHREE PHASES OF OUTPUT SIGNALS, FOR CONTROLLING THE DIRECT CURRENTOUTPUT POWER FROM SAID SOURCE APPLIED TO SAID POWER TRANSISTORS TOPRODUCE OUTPUT POWER TO A LOAD IN ACCORDANCE WITH VARIATIONS OF THETHREE PHASE SEQUENCE.